Electronic Lab - I.N.F.N. Cagliari

PMchip

Year 1993
Designers A. Lai,
L. Musa
Technology ES2 CMOS 1.0 µm
Size 75 mm2
(8.2 x 9.2)

 

The PMChip (Pipeline Memory Chip) is a VLSI custom device that squeezes an 8Kx8 pipeline memory, a 256x8 FIFO memory and all the high speed control circuits inside 75 mm2 of silicon. 
Important advantages of the VLSI approach are the following:

  • All the high frequency operations (40 MHz) are confined inside the chip. This gives more electrical and logical safety to the overall system.
  • We had the possibility to add a number of useful application-specific features, basically connected to the monitoring of the correct operation of memories during data taking and the suppression of the channels without relevant data, which would not be possible in a discrete-component system.

The PMChip has five main logical units:

  • Code Receiver Unit;
  • Data Flag Unit;
  • Memory Management Unit;
  • Pipeline Memory Unit;
  • Data Buffer Unit.

In particular The PMU has been implemented by using 8 interleaved 1Kx8 single port memory banks. This structure allows simultaneous write and read operations by simply accessing different banks in the same cycle even if the single access takes more than 25 ns. 
Internal memory arbitration is made transparent to the user by means of the MMU.

 

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