Pipeline Memory Board
From an architectural point of view, a PMB consists of a scalar part, i.e. the Board Controller (BC) and the VME interface, and a vectorial part, the 8 acquisition channels.
The DAQ channels are based on a custom VLSI circuit, named PMChip (Pipeline Memory Chip) . Each DAQ channel is implemented on three PMChips. The BC is implemented on two Xilinx programmable gate arrays.
Both the controller and the acquisition channels work synchronously under the master clock frequency of 40 MHz. The DAQ channels usually perform the same operations simultaneosly under the control of the BC. The BC can also control one single channel at a time. This is useful for test purposes, expecially during the interspill time. During data collection, each DAQ channel can receive digitized words (24 bits per channel) continuosly at 40 MHz and stores them onto a RAM.
Analog boards, performing shaping and digitization of the input signals, can be directly plugged on the PMB mother board as daughter boards (one per channel) to measure the time and amplitude of the signals. Alternatively, different kinds of daughter boards can also be plugged: as an example, it is possible to plug simple digital daughter boards with ECL receivers and ECL to TTL traslators to use the PMB logic as a general purpose pattern unit.
The DAQ channel contains:
- a circular memory (RAM) 8k time slots deep times 24 bits wide;
- a linear buffer (FIFO), 256 locations deep, where data can be transferred on a trigger request;
- the whole address control logic to authomatize read and write operations.