NA48 is a CERN experiment on the SPS k12 beam-line which is taking data since 1996 to study direct CP violation in the neutral kaon system.
For details and documentation about the experiment, please refer to the NA48 CERN homepage.
NA48 basically aims to increase the accuracy in the measurement of the epsi'/epsi parameter to the level of 2*10-4. The systematics are reduced by using two concurrent KL and KS beams. The reduction of the statistical error requires about 4.5 millions of K0l -> pi0pi0 decays, which is a decay channel with a branching ratio of the order of 10-3. For this reason, NA48 works with a high intensity beam. Anyway, an efficient use of this beam intensity requires, besides tight conditions on the detector, a DAQ system able to readout the triggered events, while a high background rate occurs, without introducing dead time. The NA48 approach is quite drastic, aiming to eliminate the trigger dead time and to reduce at a negligible level the readout dead time. A dead time free data acquisition (DAQ) and trigger system can be in principle realized by basing its design on a fully pipelined architectural approach.
Within this architectural scheme, the Cagliari group has contributed in building the complete read out systems for a number of scintillator-counter based detectors:
- Charged hodoscope (128)
- Neutral hodoscope (32 channels)
- Gamma anti-counters (144 channels)
- KS beam anticounter (AKS).
The system is based on the so-called PMBs (Pipeline Memory Boards) which are based on a custom VLSI circuit named PMChip (Pipeline Memory Chip) and on the DRM (Data Routing Module). The same PMB boards are used as pattern units to monitor the trigger performance at various stages. Both PMB and DRM boards, as well as the PMChip, were developed in our laboratories.
PMB system overview
Eight DAQ channels are housed in one PMB. A crate of PMBs (up to about 130-140 channels) is controlled by a DRM. An arbitrary number of PMBs' crates can be linked together by daisy-chaining two or more DRMs via a special ECL data bus, based on the DT32 protocol, capable of 40 MBytes/s of transfer speed. The DRM interfaces the DAQ channels of one crate with the Control Crate. The tasks of the Control crate are the following:
- It receives the trigger control words from the Trigger Supervisor and dispatches them to the DRMs. This task is performed by the Trigger Interface Controller (TIC) module.
- It collects pre-formatted data from the DRMs, completes formatting and sends data to the PC Farm (event builder). This task is performed by the Read Out Controller (ROC) module. Besides the DT32 ring, the DAQ channels crates are linked together also through a proper number of VME crate repeater.
This allows to control each single DAQ channel by means of a Single Board Computer (SBC), a CES FIC8234/43. This is necessary when initializing the system and for monitor and test operations performed during the interspill time, when data taking is suspended. The SBC can also access PMBs' data with a much slower protocol than the one used in normal data taking, by using TIC, ROC and DRMs.
The ROC and TIC modules are built using the same boards:
- the commercial CES RIO 8260 RISC I/O processor board;
- the RIO-TIC/DAT card, which is a multi purpose interface card attached to the RIO.
- The TAXI Receiver card (only in the TIC). This is used to receive the Time Stamp information from the Trigger Supervisor in a serial format and reconfigure the data in two 32 bit words, accessible by the RIO for further distribution.
The module can be programmed as a RIO-TIC (time stamp distributor), or as a RIO-DAT (data acquisition). This ROC and TIC modules are used as Read Out Controller in all the NA48 sub-detectors, exception made for the Drift Chambers and the Muon veto).