Electronic Lab - I.N.F.N. Cagliari

MARC

Muon Arm Readout Chip

 

Year 2000
Designers S. Mancini,
D. Marras,
G. Usai
Technology CMOS AMS 0.6 µm
Size 10 mm2


MARC contains the control logic for the acquisition of 64 channels (4 GASSIPLEX with 16 channels each) to drive 2 serial ADC with 12 bits resolution. It performs zero suppression and sends data to the next readout level. 

Pedestals for the zero suppression are stored in a RAM (64 words of 12 bits each). Data over threshold are then temporarily stored in a FIFO (64words of 18 bits each) together with the corresponding channel address. 

The whole 32 bits word (12 bits for the data, 6 for the channel address, 11 for the module address, 2 for the control and 1 parity bit) is then transmitted to the next stage through a serial bi-directional 4 bits link, named LINKPORT, at a speed of 20Mb/s. This link is also used for the MARC setup and for the pedestal loading in the RAM memory. 

The clock frequency for MARC running is 80 MHz and is obtained from a 16 MHz clock using a PLL, entirely designed by the INFN Cagliari group. 

Chip is produced in around 15000 samples.

 

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