Electronic Lab - I.N.F.N. Cagliari

KPIX

Year 2000
Designers S. Cadeddu,
A. Lai
Technology CMOS AMS 0.6 µm
Size 69 mm2
(16 x 4.3)
Related Projects CP16


KPix is designed to read out the analog information from pixels' matrix detectors.

A matrix of 128 amplifier × 8 columns (for a total of 1024 amplifiers) is integrated on the chip. In a column, the channel pitch is 110 µm while the column pitch is 525 µm.

Each channel is equipped with a Charge Sensitive Amplifier that collects detector charges, and with a small buffer for readout. The output of each channel is a voltage level that is multiplexed onto 10 bits ADC's with SAR (Successive Approximation Register) placed at the end of each column. The ADC outputs are then multiplexed to have 10 bits as an output of the chip. The analog lines of each column are multiplexed again and, through an analog buffer, go out of the chip. It's possible to select the kind of output to use: digital, analog or both.

The integration phase starts and stops at the same time for all channels, while the readout is made row by row starting from the left-up channel and ending with the right-down one.
The channel circuits are full custom, while the ADC's, the analog output buffer and the control logic are based on AMS library cells.

 

References

For further information, please take a look at the documents below.

 

Papers

  • S. Cadeddu, A. Lai, M. Caria – “KPIX: a pixel detector imaging chip” - NIM A 487 (2002) 175-180

 

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