Electronic Lab - I.N.F.N. Cagliari


Interpolated Time-to-Digital Converter with Auto-Calibration


Year 2010
Designers S. Cadeddu,
A. Lai
Technology CMOS UMC 90 nm
Size 2.96 mm2
(1.76 x 1.76)

The chip ITAC is designed in UMC 90nm CMOS technology.

Three different TDC scheme are implemented to verify their performance in deep sub-micron technologies. All the three schemes are based on a PLL generating a clock up to 1 GHz, starting from an external 40 MHz clock. A method for auto calibrated tapped-delay lines used in Time Interval measurements with interpolation is implemented.




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