Electronic Lab - I.N.F.N. Cagliari

Integrated Circuits

Several VLSI Integrated Circuits were developed for the experiments on which our department was involved. In the table below the main devices information are reported. For further information, see the dedicated pages.

 

Name Year Technology Die Size Designers
nSYNC 2016 UMC CMOS
130 nm
16.7 mm2
(4.4 x 3.8)

S. Cadeddu,
L. Casu,
A. Lai,
A. Loi

 

ADV2 2015 UMC CMOS
130 nm
2.2 mm2
(1.5 x 1.5)

S. Cadeddu,
A. Lai

 

ADV1 2013 UMC CMOS
130 nm
2.2 mm2
(1.5 x 1.5)

S. Cadeddu,
A. Lai

 

SENSI+1 2013 UMC CMOS
180 nm
3 mm2
(1.8 x 1.8)

S. Cadeddu,
A. Lai,
V. Sipala,
Dip. IE Pisa,
Dip. IE Padova,
Dip. IE Roma2

 

PRIMA+ 2012 AMS CMOS
0.35 µm
17 mm2
(2.3 x 8)

S. Cadeddu,
A. Lai,
V. Sipala

 

ITAC
(Interpolated Time-to-Digital Converter with Auto-Calibration)

 

2010 UMC CMOS
90 nm
2.96 mm2
(1.76 x 1.76)
S. Cadeddu,
A. Lai
SYNC 2004 IBM CMOS
0.25 µm
16 mm2
(4 x 4)

S. Cadeddu,
C. Deplano,
V. De Leo,
A. Lai

 

DIALOG
DIagnostics time Adjustment and LOGics
2004 IBM CMOS
0.25 µm
19 mm2
(3.9 x 4.9)

S. Cadeddu,
C. Deplano,
A. Lai

 

KPIX 2000 AMS CMOS
0.6 µm
69.03 mm2
(16 x 4.3)

S. Cadeddu,
A. Lai

 

MARC
M
uon Arm Readout Chip
2000 AMS CMOS
0.6 µm
10 mm2

S. Mancini,
D. Marras,
G. Usai

 

CP16
C
urrent Preamplifier 16 channels
1999 AMS CMOS
0.6 µm
2.5 mm2
(1 x 2.5)

S. Cadeddu,
A. Lai

 

PHAROS
P
ulse Height Analyzer and ReadOut System
1999 AMS BiCMOS
0.8 µm
16 mm2
(3 x 5.4)

S. Cadeddu,
D. Caredda,
A. Lai,

 

PHAnTIC
P
ulse Height Analyzer Test Integrated Chip
1998 AMS CMOS
0.8 µm
1.6 mm

D. Caredda,
A. Lai

 

ChromatIC 1997 ES2 CMOS
0.7 µm
34 mm2
(6.4 x 5.3)

S. Cadeddu,
A. Lai,
P. Porcu

 

PMChip
Pipeline Memory Chip
1993 ES2 CMOS
1.0 µm
72 mm2
(8.2 x 9.2)

A. Lai,
L. Musa

 

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