Electronic Lab - I.N.F.N. Cagliari

DIALOG

Year 2004
Designers S. Cadeddu,
C. Deplano,
A. Lai
Technology CMOS IBM 0.25 µm
Rad Hard
Size 19 mm2
(3.9 x 4.9)
Related Projects SYNC

 

DIALOG (DIagnostic, time Adjustment and LOGics) is a custom integrated circuit dedicated to the Muon Detector of the Large Hadron Collider beauty (LHCb) experiment at the CERN Large Hadron Collider. It is developed in IBM 0.25 μm technology. By using specific layout techniques, this technology provides good radiation resistance, able to sustain an accumulated dose of several Mrad. For the muon detector, the maximum accumulated dose during ten years of LHCb operation is estimated to be about 1 Mrad.

On the front-end boards, one DIALOG serves two ASD (Amplifier, Shaper, Discriminator), for a total of 16 front-end input channels. Each single input channel can be delayed by 0 to 31 programmable steps. Each step adds a delay of about 1.6 ns provided by a Voltage Controlled Delay Line. All input channels are reshaped in width using a programmable digital shaper. A mask is foreseen for the selection (or de-selection) of each input channel. The specific logic function used to generate the Logical Channels is written on dedicated registers accessed by the I2C bus interface. The possible logic combinations are:

  • logic OR of 2, 4 or 8 input channels
  • logic OR of 2 (4) signals that are the logic AND of 2 input channels

DIALOG provides 18 independent threshold signals for the ASD discriminators, using an integrated 8-bit DAC (Digital to Analog Converter) and a linear output driver for each threshold level.

All DIALOG facilities are configured by the I2C interface and the control data are stored inside 93 8-bit registers.

DIALOG key features:

  • Programmable input signals time adjustment (0-31 steps of ~ 1.6 ns)
  • External selection or automatic calibration by DLL (settable period ~ 59 ns ÷ 21 ns)
  • Mask on every input channel
  • Programmable output signals width adjustment (8 step of ~ 3 ns each)
  • 2 ASD pulse generation signals with programmable time adjustment
  • Logical Channel generation
    • OR2; OR4; OR8;
    • AND2; OR2(2AND2); OR4(4AND2)
  • Internal trigger-able Pattern generation
  • Sixteen 24 bits rate counters
  • 18 different threshold signals for ASD
  • I2C interface (93 registers)
  • Triple-voted and auto-corrected register for better SEU immunity (both configuration and state machines)

 

References

For further information, please take a look at the documents below.

 

Papers

  • S. Cadeddu, V. De Leo, C. Deplano, A. Lai – “Instruments and procedures for time calibration of the LHCb muon detector” – NIM A 589 (2008) 404-414
  • S. Cadeddu, V. De Leo, C. Deplano, E. Fois, A. Lai –  “Time Calibration of the LHCb Muon System” – 2006 Nuclear Science Symposium 186-189
  • S. Cadeddu, V. De Leo, C. Deplano, A. Lai –  “A test bench for full characterization of the DIALOG chip” – 2005 Nuclear Science Symposium 665-669
  • S. Cadeddu, C. Deplano, A. Lai – “The DIALOG chip in the front-end electronics of the LHCb muon detector” – IEEE TNS vol. 52:2726-2732, 2005
  • S. Cadeddu, V. De Leo, C. Deplano, A. Lai –  “DIALOG and SYNC : a VLSI chip set for timing of the LHCb Muon detector”- IEEE TNS vol. 51 n 5 October 2004
  • S. Cadeddu, V. De Leo, C. Deplano, A. Lai –  “DIALOG: an ASIC for timing of the LHCb muon detector” – NIM A 518 (2004) 486-490

 

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